Generally, a clock signal is an important signal in electronic systems, and a frequency is an important characteristic of a clock signal. In modern VLSI systems, various functional blocks operate at their own clock rates. In most cases, these different clock rates are related to each other through a fixed ratio. As a result, frequency division is a critical issue in electronic system designs.
In electronic system designs, it is often required to divide the frequency of a high frequency signal (e.g., a source frequency) to a low frequency signal (e.g., a destination frequency). Typically, integer frequency division can be easily realized. If the divide ratio is an integer, a conventional frequency divider may be used, in which the divide ratio is expressed by the following equation:fout=fin/N  (1)where N is an integer.
However, if the divide ratio is a non-integer (e.g., a fraction), the conventional frequency divider cannot achieve the desired result. For example, if a source frequency is 2475 MHz (e.g., a RF carrier) and a destination frequency is 2 MHz (e.g., a baseband clock signal), thus the ratio between the two (e.g., 2475/2) is equal to 1237.5, which is a non-integer. Fractional frequency division is a nontrivial task, and is traditionally achieved through a phase locked loop (PLL).
FIG. 1 shows a diagram of a conventional integer-N PLL 100 using a feedback mechanism. Conventionally, the integer-N PLL 100 is used to achieve the fractional frequency division, in which:fd=(N/[P*M])*fs  (2)where fs and fd are the source and destination frequencies, respectively, where fs is the source frequency, fd is the destination frequency, P is the divide ratio of /P divider 110, N is the divide ratio of /N divider 160, and M is the divide ratio of /M divider 150. Typically, P, N and M are integers. Thus, the resulting division ratio (fs/fd) may be expressed by the following equation:fs/fd=(P*M)/N  (3)where (P*M)/N is a number that can be a fraction. Thus, the resulting division ratio fs/fd may be expressed as in Equation (3) above, and accordingly, a fractional ratio may be obtained from (M*P)/N.
In FIG. 1, phase frequency detector 120 detects the frequency and/or phase difference between the input clock signal 115 and feedback signal 165, and outputs an offset signal 125 to a low pass filter 130. Subsequently, the filter 130 smoothes the offset signal 125, and outputs an adjustment signal 135 to a voltage controlled oscillator (VCO) 140. The VCO 140 outputs a periodic signal 145 to (i) a divide-by-M divider 150 and (ii) a divide-by-N divider 160, where M and N are integers and are constant. Divider 150 outputs a frequency-divided clock signal 155, and the divider 160 outputs a feedback signal 165 to the phase detector 110 for comparison with the clock signal 115.
FIG. 2 shows a diagram of a conventional fractional-N PLL 100′ using a feedback loop. Using fractional-N PLL 100′, a divide-by-N·r divider 162 is a number having a fractional portion, in which N is the integer part and r is the fractional part. More fractional division ratios are available using PLL 100′, as expressed in the following equation:fs/fd=(P*M)/(N·r)  (4)
Thus, the resulting division ratio of PLL 100′ is expressed in Equation (4) above. In this configuration, the integer divider inside the loop can dynamically switch its division ratio. On average, the actual ratio achieved is N·r, where N is the integer part and r is the fractional part. Based on Equation (4) above, almost any fractional division ratio may be realized.
One of the issues with using a PLL is the cost in power and area. Additionally, unlike a counter, which directly divides the frequency down, the frequency ratio generated from a PLL contains a certain degree of error since it uses feedback. Feedback is an indirect, compare-then-correct approach. Thus, the feedback mechanism (e.g., the compare-then-correct mechanism) inevitably introduces some degree of frequency inaccuracy. Another technique popular in wireless applications is the use of an injection-locked fractional frequency divider.
This “Discussion of the Background” section is provided for background information only. The statements in this “Discussion of the Background” are not an admission that the subject matter disclosed in this “Discussion of the Background” section constitutes prior art to the present disclosure, and no part of this “Discussion of the Background” section may be used as an admission that any part of this application, including this “Discussion of the Background” section, constitutes prior art to the present disclosure.